Sun 23 Jun 2019 11:00 - 11:45 at 106B - HW/SW Interface Specifications Chair(s): Adam Chlipala

The RISC-V community is perhaps unique in pushing for an early formal specification of the RISC-V ISA (Instruction Set Architecture), and to declare an intention that it will become the definitive spec of the ISA. A task group was set up within the RISC-V Foundation to develop this spec, with active contributions and participation from about a dozen organizations, representing academia and industry. The speaker (who chaired this group) will describe the technical and process challenges in converging on a community-driven, open, non-proprietary, industrial-strength ISA spec.

Sun 23 Jun

Displayed time zone: Tijuana, Baja California change

11:00 - 12:30
HW/SW Interface SpecificationsDeepSpec at 106B
Chair(s): Adam Chlipala Massachusetts Institute of Technology, USA
11:00
45m
Talk
Development of the RISC-V ISA Formal Specification
DeepSpec
11:45
45m
Talk
Automated Formal Memory Consistency Verification of Hardware
DeepSpec
Yatin Manerkar Princeton University