High-Level Synthesis of Functional Patterns with Lift
High-level languages are commonly seen as a good fit to tackle the problem of performance portability across parallel architectures. The Lift framework is a recent approach which has successfully demonstrated its ability to address the challenge of performance portability across multiple types of CPU and GPU devices. The functional and pattern-based nature of Lift simplifies the optimization of programs using rewrite-rules. In this work we extend Lift to target FPGA-based platforms. We designed parallel patterns operating on data stream, and we implemented a Lift to VHDL backend. This contribution has been evaluated on a Xilinx XC7Z010 FPGA, using matrix multiplication for which we observe up to 10x speed-up over highly optimized CPU code and a commercial HLS tool. Furthermore, by considering the potential of design space exploration enabled by Lift, this work is a stepping stone towards automatically generated competitive code for FPGAs.
Sat 22 Jun
|16:00 - 16:30|
|16:30 - 17:00|
|17:00 - 17:30|