Sat 22 Jun 2019 17:00 - 17:30 at 106C - Session 5 Chair(s): Lenore Mullin

High-level languages are commonly seen as a good fit to tackle the problem of performance portability across parallel architectures. The Lift framework is a recent approach which has successfully demonstrated its ability to address the challenge of performance portability across multiple types of CPU and GPU devices. The functional and pattern-based nature of Lift simplifies the optimization of programs using rewrite-rules. In this work we extend Lift to target FPGA-based platforms. We designed parallel patterns operating on data stream, and we implemented a Lift to VHDL backend. This contribution has been evaluated on a Xilinx XC7Z010 FPGA, using matrix multiplication for which we observe up to 10x speed-up over highly optimized CPU code and a commercial HLS tool. Furthermore, by considering the potential of design space exploration enabled by Lift, this work is a stepping stone towards automatically generated competitive code for FPGAs.

Sat 22 Jun
Times are displayed in time zone: (GMT-07:00) Tijuana, Baja California change

16:00 - 17:30: ARRAY 2019 - Session 5 at 106C
Chair(s): Lenore MullinSUNY Albany, USA
ARRAY-2019-papers16:00 - 16:30
Dejice Jacob, Jeremy SingerUniversity of Glasgow
ARRAY-2019-papers16:30 - 17:00
Henrik BarthelsRWTH Aachen, Paolo BientinesiUmeƄ University
ARRAY-2019-papers17:00 - 17:30
Martin KristienUniversity of Edinburgh, UK, Bruno BodinYale-NUS College, Michel SteuwerUniversity of Glasgow, Christophe DubachUniversity of Edinburgh